SR latch
From Rice Wiki
The set-reset latch is a circuit that stores a value in a bistable circuit using two NOR gates. It is the fundamental building block for memory cells.
An enabler can be integrated with AND gates. By fluctuating the enabler at set time intervals, we get a clocked D-latch.
Note that it is an abstraction and may be astable
The D-latch acts on level. This messes up the clock cycle.
