http://ricefriedegg.com:80/mediawiki/index.php?action=history&feed=atom&title=D_latchD latch - Revision history2026-05-26T22:24:02ZRevision history for this page on the wikiMediaWiki 1.41.0http://ricefriedegg.com:80/mediawiki/index.php?title=D_latch&diff=731&oldid=prevRice at 19:31, 17 May 20242024-05-17T19:31:46Z<p></p>
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</table>Ricehttp://ricefriedegg.com:80/mediawiki/index.php?title=D_latch&diff=668&oldid=prevRice: Created page with "Figure 1. Schematic of a D latch The '''D latch''' is a direct upgrade from an SR latch. It has two inputs: (D)ata and (E)nabler. When ''E'' is activated, ''D'' is stored into the latch. When the enabler is deactivated, the circuit continues to latch the current value regardless of ''D''. = Clocked D latch = By connecting a clock to the enabler, you get a '''clocked D latch''' that is synchronized with the rest of the circuit. This is..."2024-05-06T22:22:01Z<p>Created page with "<a href="/mediawiki/index.php/File:D_latch.png" title="File:D latch.png">thumb|Figure 1. Schematic of a D latch</a> The '''D latch''' is a direct upgrade from an <a href="/mediawiki/index.php/SR_latch" title="SR latch">SR latch</a>. It has two inputs: (D)ata and (E)nabler. When ''E'' is activated, ''D'' is stored into the latch. When the enabler is deactivated, the circuit continues to latch the current value regardless of ''D''. = Clocked D latch = By connecting a <a href="/mediawiki/index.php?title=Clock&action=edit&redlink=1" class="new" title="Clock (page does not exist)">clock</a> to the enabler, you get a '''clocked D latch''' that is synchronized with the rest of the circuit. This is..."</p>
<p><b>New page</b></p><div>[[File:D latch.png|thumb|Figure 1. Schematic of a D latch]]<br />
The '''D latch''' is a direct upgrade from an [[SR latch]]. It has two inputs: (D)ata and (E)nabler. When ''E'' is activated, ''D'' is stored into the latch. When the enabler is deactivated, the circuit continues to latch the current value regardless of ''D''.<br />
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= Clocked D latch =<br />
By connecting a [[clock]] to the enabler, you get a '''clocked D latch''' that is synchronized with the rest of the circuit. This is useful in ensuring that the ''D'' written to the .<br />
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An enabler can be integrated with AND gates. By fluctuating the enabler at set time intervals, we get a '''clocked D-latch'''.<br />
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Note that it is an ''abstraction'' and may be [[astable]]<br />
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The D-latch acts on level. This messes up the clock cycle.</div>Rice