ISA - Revision history

Rice: /* RISC */

2024-05-20T15:46:24Z

RISC

← Older revision		Revision as of 15:46, 20 May 2024
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	= RISC =		= RISC =
	Reduced instruction set computer forbids arithmetic instructions from accessing memory. Instead, we get more registers. Only the most commonly used instructions are implemented, each instructoin taking 3 operands.		Reduced instruction set computer forbids arithmetic instructions from accessing memory. Instead, we get more registers. Only the most commonly used instructions are implemented, each instructoin taking 3 operands.

			It is fast because of the common components being fast (such as decoder).

	For example, ARM stands for Advanced Risc Machine		For example, ARM stands for Advanced Risc Machine

Rice: /* RISC */

2024-05-20T15:34:50Z

RISC

← Older revision		Revision as of 15:34, 20 May 2024
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	= RISC =		= RISC =
	Reduced instruction set computer forbids arithmetic instructions from accessing memory. Instead, we get more registers. Only the most commonly used instructions are implemented.		Reduced instruction set computer forbids arithmetic instructions from accessing memory. Instead, we get more registers. Only the most commonly used instructions are implemented, each instructoin taking 3 operands.

	For example, ARM stands for Advanced Risc Machine		For example, ARM stands for Advanced Risc Machine

Rice: /* CISC */

2024-05-20T15:34:17Z

CISC

← Older revision		Revision as of 15:34, 20 May 2024
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	= CISC =		= CISC =
	Complex instruction set computer has many instructions and multiple addressing modes. This makes for fewer instructions per program but complex data path.		Complex instruction set computer has many instructions and multiple addressing modes. This makes for fewer instructions per program but complex data path.

			For example, intel cores.

			= RISC =
			Reduced instruction set computer forbids arithmetic instructions from accessing memory. Instead, we get more registers. Only the most commonly used instructions are implemented.

			For example, ARM stands for Advanced Risc Machine

Rice: /* Accumulator */

2024-05-20T15:29:51Z

Accumulator

← Older revision		Revision as of 15:29, 20 May 2024
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	= Accumulator =		= Accumulator =
	One operand is a register called accumulator, the other is from memory. Acc is always destination, so it is a one-address architecture.		One operand is a register called accumulator, the other is from memory. Acc is always destination, so it is a one-address architecture.

			The bottleneck is Acc, which everything goes through, making it slow.

			= CISC =
			Complex instruction set computer has many instructions and multiple addressing modes. This makes for fewer instructions per program but complex data path.

Rice: /* Stack */

2024-05-20T15:25:19Z

Stack

← Older revision		Revision as of 15:25, 20 May 2024
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	It has the downside of being slow due to DRAM being slower than SRAM.		It has the downside of being slow due to DRAM being slower than SRAM.

			= Accumulator =
			One operand is a register called accumulator, the other is from memory. Acc is always destination, so it is a one-address architecture.

Rice: Created page with "Category:Computer Architecture '''Instruction set architecture (ISA)''' = Stack = Zero address architecture, where operands are on stack inside CPU. It has the downside of being slow due to DRAM being slower than SRAM."

2024-05-20T15:22:28Z

Created page with "Category:Computer Architecture '''Instruction set architecture (ISA)''' = Stack = Zero address architecture, where operands are on stack inside CPU. It has the downside of being slow due to DRAM being slower than SRAM."

New page

[[Category:Computer Architecture]]

'''Instruction set architecture (ISA)'''

= Stack =
Zero address architecture, where operands are on stack inside CPU.

It has the downside of being slow due to DRAM being slower than SRAM.