Virtual memory - Revision history

Rice at 02:02, 7 June 2024

2024-06-07T02:02:56Z

← Older revision		Revision as of 02:02, 7 June 2024
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	* Miss == Page fault		* Miss == Page fault
	* Tag == Virtual page number		* Tag == Virtual page number

			= Page table =
			Page tables are used to translate virtual address into physical address. It is usually stored in physical memory due to its size. This means that a virtual memory access normally requires 2 main memory accesses: translation and access.

			== Translation lookaside buffer ==
			The TLB is a small cache that stores the most recent translations to reduce the number of memory accesses. Because page accesses have high temporal locality, where consecutive loads and stores are likely to access the same page due to the page size being large, TLB is fully associative.

	= Memory protection =		= Memory protection =

2024-06-07T01:57:47Z

← Older revision		Revision as of 01:57, 7 June 2024
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	Virtual memory gives the illusion of a bigger memory. Each programs use the same virtual addresses.		Virtual memory gives the illusion of a bigger memory by making memory acts as a cache for hard disk storage.

			= Functionality =
			Each programs use the same set virtual addresses. That is, two programs can have the same virtual addresses.

			The entire address space will be stored on hard drive, but a subset would be in main memory. The CPU translates the virtual addresses into DRAM addresses, and if the address you're looking for is not there, it is fetched from the hard drive.

			= Compare to cache =
			A lot of concepts here are the same as in [[cache]]s:
			* Block == Page
			* Miss == Page fault
			* Tag == Virtual page number

			= Memory protection =
			A good thing about virtual memory is that because each program has their own virtual address table, memory protection can be easily enforced, where a malicious program cannot corrupt the memory of another program.

			= Archived notes =

	Physical memory acts as a cache for virtual memory. A '''page table''' can be used to translate virtual to physical address.		Physical memory acts as a cache for virtual memory. A '''page table''' can be used to translate virtual to physical address.

2024-06-05T15:50:31Z

← Older revision		Revision as of 15:50, 5 June 2024
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	A '''translation lookaside buffer (TLB)''' is a small cache of recent translations that reduces memory accesses. Page tables are high temporal locality so fully associative.		A '''translation lookaside buffer (TLB)''' is a small cache of recent translations that reduces memory accesses. Page tables are high temporal locality so fully associative.

	Each process has a page tables that only maps to one section of physical address. The OS prevents accesses from one process to another.		Each process has a page tables that only maps to one section of physical address. The OS prevents accesses from one process to another. When processes switch, we either store a process id or to just flush the page tables.



	[[Category:Computer Architecture]]		[[Category:Computer Architecture]]

2024-06-05T15:49:46Z

← Older revision		Revision as of 15:49, 5 June 2024
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	A '''translation lookaside buffer (TLB)''' is a small cache of recent translations that reduces memory accesses. Page tables are high temporal locality so fully associative.		A '''translation lookaside buffer (TLB)''' is a small cache of recent translations that reduces memory accesses. Page tables are high temporal locality so fully associative.

			Each process has a page tables that only maps to one section of physical address. The OS prevents accesses from one process to another.



	[[Category:Computer Architecture]]		[[Category:Computer Architecture]]

2024-06-05T15:48:10Z

← Older revision		Revision as of 15:48, 5 June 2024
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	Most accesses hits physical memory, but some doesn't.		Most accesses hits physical memory, but some doesn't.

	A '''translation lookaside buffer''' is a small cache of recent translations that reduces memory accesses. Page tables are high temporal locality so fully associative.		A '''translation lookaside buffer (TLB)''' is a small cache of recent translations that reduces memory accesses. Page tables are high temporal locality so fully associative.



	[[Category:Computer Architecture]]		[[Category:Computer Architecture]]

2024-06-05T15:47:28Z

← Older revision		Revision as of 15:47, 5 June 2024
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	Most accesses hits physical memory, but some doesn't.		Most accesses hits physical memory, but some doesn't.

	A '''translation lookaside buffer''' is a small cache of recent translations that reduces memory accesses.		A '''translation lookaside buffer''' is a small cache of recent translations that reduces memory accesses. Page tables are high temporal locality so fully associative.



	[[Category:Computer Architecture]]		[[Category:Computer Architecture]]

2024-06-05T15:46:43Z

← Older revision		Revision as of 15:46, 5 June 2024
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	Most accesses hits physical memory, but some doesn't.		Most accesses hits physical memory, but some doesn't.

			A '''translation lookaside buffer''' is a small cache of recent translations that reduces memory accesses.



	[[Category:Computer Architecture]]		[[Category:Computer Architecture]]

2024-06-05T15:38:34Z

← Older revision		Revision as of 15:38, 5 June 2024
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	Virtual memory gives the illusion of a bigger memory. Each programs use the same virtual addresses.		Virtual memory gives the illusion of a bigger memory. Each programs use the same virtual addresses.

	Physical memory acts as a cache for virtual memory.		Physical memory acts as a cache for virtual memory. A '''page table''' can be used to translate virtual to physical address.

			Most accesses hits physical memory, but some doesn't.

	[[Category:Computer Architecture]]		[[Category:Computer Architecture]]

2024-06-05T15:35:37Z

← Older revision		Revision as of 15:35, 5 June 2024
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	Virtual memory gives the illusion of a bigger memory. ~~Programs~~ use virtual addresses.		Virtual memory gives the illusion of a bigger memory. Each programs use the same virtual addresses.

			Physical memory acts as a cache for virtual memory.
	[[Category:Computer Architecture]]		[[Category:Computer Architecture]]

2024-06-05T15:34:08Z

Created page with "Virtual memory gives the illusion of a bigger memory. Programs use virtual addresses. Category:Computer Architecture"

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Virtual memory gives the illusion of a bigger memory. Programs use virtual addresses.
[[Category:Computer Architecture]]