ARM/Instruction format: Difference between revisions
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[[Category:Computer Architecture]] | [[Category:Computer Architecture]] | ||
The ARM instruction format is split into three types of instructions: | |||
* [[ARM/Data-processing instruction]] | |||
* [[ARM/Memory instruction]] | |||
* [[ARM/Branch instruction]] | |||
This page will go through the instruction format of each type. | |||
= Data-processing instruction format = | |||
Data-processing instructions take in the following operands | |||
* '''Rn:''' the first source register | |||
* '''Src2:''' the second source, which may be register or [[ARM/immediate|immediate]] | |||
* '''Rd:''' destination register | |||
and the following is used to control the instruction | |||
* '''cond:''' specifies [[ARM/conditional execution|conditional execution]] (31:28) | |||
* '''op:''' the opcode, which is 0b00 for data processing instructions (27:26) | |||
* '''funct:''' the function to perform (25:20) | |||
== Control fields == | |||
For all data processing instructions, the opcode is 0b00. The exact operation is specified by the '''funct'''. | |||
The funct field is further split into three subfields: | |||
* '''I''' is a one-bit field that specifies whether src2 is an [[ARM/immediate|immediate]]. | |||
* '''cmd''' specifies which DP operation is performed | |||
* '''S''' is a one-bit field that specifies whether to set condition flags. | |||
== Src2 == | |||
This 12-bit field can represent an immediate, a constant-shifted register, or a register-shifted register. | |||
* Immediate: rot4 imm8 | |||
* Register: shamt5 sh2 0 Rm | |||
* Register shifted register: Rn 0 sh2 1 Rm | |||
= Src2 = | = Src2 = | ||
| Line 5: | Line 40: | ||
The immediate is rotated imm8 ROR rot*2, limiting precision but allowing for a greater range of values. | The immediate is rotated imm8 ROR rot*2, limiting precision but allowing for a greater range of values. | ||
= Memory instruction format = | |||
Memory instructions have the following fields | |||
* '''op:''' 01 | |||
* '''Rn:''' base register | |||
* '''Rd:''' destination (load), source (store). Holds the actual loaded/stored value. | |||
* '''Src2''': offset | |||
* '''funct''': 6 control bits | |||
== Control bits == | |||
Control bits determine which memory instruction is being executed | |||
* '''I''' bar: immediate bar, determine offset type | |||
* '''P''': Preindex (offset is added to address before accessing) | |||
* '''U''': Add (determine whether offset is added or subtracted) | |||
* '''B''': Operate with Bytes | |||
* '''W''': Writeback (address accessed is wrote to register) | |||
* '''L''': Operation is load instruction (store if 0) | |||
= Branch instruction = | |||
It's literally just an L and some immediates. L is for linking and jumping back. | |||
Latest revision as of 20:18, 28 May 2024
The ARM instruction format is split into three types of instructions:
This page will go through the instruction format of each type.
Data-processing instruction format
Data-processing instructions take in the following operands
- Rn: the first source register
- Src2: the second source, which may be register or immediate
- Rd: destination register
and the following is used to control the instruction
- cond: specifies conditional execution (31:28)
- op: the opcode, which is 0b00 for data processing instructions (27:26)
- funct: the function to perform (25:20)
Control fields
For all data processing instructions, the opcode is 0b00. The exact operation is specified by the funct.
The funct field is further split into three subfields:
- I is a one-bit field that specifies whether src2 is an immediate.
- cmd specifies which DP operation is performed
- S is a one-bit field that specifies whether to set condition flags.
Src2
This 12-bit field can represent an immediate, a constant-shifted register, or a register-shifted register.
- Immediate: rot4 imm8
- Register: shamt5 sh2 0 Rm
- Register shifted register: Rn 0 sh2 1 Rm
Src2
Allows for immediate (a constant with rotation), register (with a static shift amount), or register-shifted register.
The immediate is rotated imm8 ROR rot*2, limiting precision but allowing for a greater range of values.
Memory instruction format
Memory instructions have the following fields
- op: 01
- Rn: base register
- Rd: destination (load), source (store). Holds the actual loaded/stored value.
- Src2: offset
- funct: 6 control bits
Control bits
Control bits determine which memory instruction is being executed
- I bar: immediate bar, determine offset type
- P: Preindex (offset is added to address before accessing)
- U: Add (determine whether offset is added or subtracted)
- B: Operate with Bytes
- W: Writeback (address accessed is wrote to register)
- L: Operation is load instruction (store if 0)
Branch instruction
It's literally just an L and some immediates. L is for linking and jumping back.
