SR latch: Difference between revisions
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Note that it is an ''abstraction'' and may be [[astable]] | Note that it is an ''abstraction'' and may be [[astable]] | ||
The D-latch acts on level. This messes up the clock cycle. | |||
[[Category:Computer Architecture]] | [[Category:Computer Architecture]] | ||
Revision as of 19:51, 29 April 2024
The set-reset latch is a circuit that stores a value in a bistable circuit using two NOR gates. It is the fundamental building block for memory cells.
An enabler can be integrated with AND gates. By fluctuating the enabler at set time intervals, we get a clocked D-latch.
Note that it is an abstraction and may be astable
The D-latch acts on level. This messes up the clock cycle.
