User contributions for Rice
From Rice Wiki
10 May 2024
- 01:1701:17, 10 May 2024 diff hist +393 N Sequential circuit Created page with "'''Sequential circuit''' is a type of circuit whose output is influenced by both current and prior inputs. = Memory = Sequential circuits have ''memory'' that record the ''state'' of the circuit depending on prior inputs. This memory is stored by '''latches''' and '''flip-flops'''. Here is a list of related components. * Category:Computer ArchitectureCategory:ECS154A Midterm"
- 01:1001:10, 10 May 2024 diff hist +28 Multiplexer No edit summary current
- 00:2900:29, 10 May 2024 diff hist +220 Multiplexer No edit summary Tag: Visual edit
- 00:2800:28, 10 May 2024 diff hist +7 N File:4-1 MUX.png No edit summary current
9 May 2024
- 22:5722:57, 9 May 2024 diff hist +194 Sum of products No edit summary current
- 22:0122:01, 9 May 2024 diff hist +109 Sum of products No edit summary
- 21:5921:59, 9 May 2024 diff hist +76 Bubble pushing No edit summary current
- 21:4821:48, 9 May 2024 diff hist −85 Karnaugh map No edit summary current
- 21:4721:47, 9 May 2024 diff hist +30 Karnaugh map →How it works
- 21:4721:47, 9 May 2024 diff hist +233 Sum of products No edit summary
- 21:4521:45, 9 May 2024 diff hist +25 Minterm No edit summary current
- 21:4421:44, 9 May 2024 diff hist +141 N Minterm Created page with "A '''minterm''' is a term that consists of all inputs, complemented or not. Category:Computer Architecture Category:ECS154A Midterm"
- 21:4121:41, 9 May 2024 diff hist +550 N Circuit Created page with "A '''circuit''' is a network that processes discrete valued inputs and outputs. Each circuit has a '''functional specification''' dictating the relationship between input and ouput. Each circuit also has a '''timing specification''' determining the delay between input changing and output changing. See Timing page for details. = Classifications = A combinational circuit's output only depends on its current input. A sequential circuit's output depends on m..." current
- 21:4021:40, 9 May 2024 diff hist +514 N Combinational circuit Created page with "A '''combinational circuit''' is a circuit whose outputs only depend on the current input. Logic gates are an example of combinational circuits. = Construction criteria = To construct a combinational circuit, the following must be met: * Each circuit element inside the circuit must be combinational. * Every node is either designated as an input or connects to exactly one output of a circuit element. * The circuit does not have cyclic paths. Category:Computer Arch..." current
- 20:2820:28, 9 May 2024 diff hist +165 Static discipline No edit summary current
- 20:2620:26, 9 May 2024 diff hist +537 N Static discipline Created page with "The '''static discipline''' is a discipline in computer architecture that requires all circuit elements to produce ''logically valid'' outputs. In the real world circuits, there is no 0's and 1's, only voltage levels. For abstraction, we interpret a range of high voltages as 1 and a range of low voltages as 0. The static discipline ensures that this abstraction doesn't run into problems/undefined behavior by forcing all circuit elements to operate on 1's and 0's. [..." Tag: Visual edit
- 20:1920:19, 9 May 2024 diff hist +373 Adder No edit summary Tag: Visual edit
- 20:1820:18, 9 May 2024 diff hist +26 N File:Full adder.png No edit summary current
- 19:5119:51, 9 May 2024 diff hist +211 Adder No edit summary
- 19:4919:49, 9 May 2024 diff hist −19 Adder No edit summary
- 19:4719:47, 9 May 2024 diff hist +19 N Add Rice moved page Add to Adder current Tag: New redirect
- 19:4719:47, 9 May 2024 diff hist 0 m Adder Rice moved page Add to Adder
- 19:4619:46, 9 May 2024 diff hist 0 N Category:ECS154A Midterm Created blank page current
- 19:4619:46, 9 May 2024 diff hist +731 N Two's complement Created page with " '''Two's complement''' is a way to represent signed integers in binary. It is more widely used than its counterpart signed magnitude due to advantages like ease of operations. = Operation = In this system, think of the first bit in the bit pattern as negative. For example, 101 would be 4 + 1 = 5 as an unsigned number, but -4 + 1 = -3 as a signed number represented by 2's complement. To negate signed numbers, flip all bits and add 1. This comes from math: <math>-2..." current
- 19:4519:45, 9 May 2024 diff hist −532 Information Representation →Signed Integers
- 19:4219:42, 9 May 2024 diff hist +274 N Discipline Created page with "There is a high amount of abstraction related to computer architecture, from physical to program. A '''discipline''' is a way to manage that complexity by intentionally limiting design choices. = Source = * Computer Architecture ARM book Category:Computer Architecture" current
- 19:3319:33, 9 May 2024 diff hist +28 Adder No edit summary
- 19:3119:31, 9 May 2024 diff hist +160 N Multiplexer Created page with "A '''multiplexer (MUX)''' takes in many inputs and a select input. Based on the select input, it outputs one specific input. Category:Computer Architecture"
8 May 2024
- 15:2715:27, 8 May 2024 diff hist +37 Timing No edit summary
- 15:1615:16, 8 May 2024 diff hist +64 Timing →Delay
- 15:1315:13, 8 May 2024 diff hist +128 N Dynamic discipline Created page with "Synchronous sequential circuit inputs must be stable during aperture time around clock edge. Category:Computer Architecture" current
- 15:1215:12, 8 May 2024 diff hist +160 Timing No edit summary
- 03:0003:00, 8 May 2024 diff hist +168 Maximum likelihood estimation →Assumptions current
- 02:5402:54, 8 May 2024 diff hist +70 Maximum likelihood estimation →Likelihood function
6 May 2024
- 22:2222:22, 6 May 2024 diff hist +772 N D latch Created page with "thumb|Figure 1. Schematic of a D latch The '''D latch''' is a direct upgrade from an SR latch. It has two inputs: (D)ata and (E)nabler. When ''E'' is activated, ''D'' is stored into the latch. When the enabler is deactivated, the circuit continues to latch the current value regardless of ''D''. = Clocked D latch = By connecting a clock to the enabler, you get a '''clocked D latch''' that is synchronized with the rest of the circuit. This is..." Tag: Visual edit
- 22:2122:21, 6 May 2024 diff hist +30 N File:D latch.png No edit summary current
- 20:2320:23, 6 May 2024 diff hist +777 SR latch No edit summary current Tag: Visual edit
- 20:2120:21, 6 May 2024 diff hist +79 N File:SR latch with not.png No edit summary current
- 20:1220:12, 6 May 2024 diff hist +25 N File:SR latch schematic.png No edit summary current
3 May 2024
- 19:3519:35, 3 May 2024 diff hist +310 N Timer Created page with "A '''timer''' is a circuit that takes in an increase in input and generates an increase in output after an amount of time passes. = Real timers = Ideally, we want an instant transition from low to high. This is impossible. Real world timers looks kinda like a sigmoid lol. Category:Computer Architecture" current
- 19:3419:34, 3 May 2024 diff hist +346 N Finite state machine Created page with "The '''state''' of the program is its memory. A '''finite state machine''' continuously computes the current state with the previous state based on a function. In a '''Moore circuit''', output only depends on the current state. In contrast, in a ''Mealy circuit''', input is also wired into the output logic. Category:Computer Architecture"
- 16:0016:00, 3 May 2024 diff hist +117 Timing →Delay Tag: Visual edit
- 15:2115:21, 3 May 2024 diff hist +694 N Timing Created page with " = Delay = The amount of time passed before the output follows the input is the propagation delay. It is the maximum delay from input to output. During this time, the output is unpredictable. Since the output is unpredictable during the time after input and before propagation delay passed, it is possible to read an output during this time. This is the contamination delay: the minimum delay from input to output. The reason for the unpredictability at contaminati..."
- 15:1915:19, 3 May 2024 diff hist +53 Critical path No edit summary current
- 15:0915:09, 3 May 2024 diff hist +112 N Propagation delay Created page with "The propagation delay is the time before which a circuit element stabilizes. Category:Computer Architecture" current
1 May 2024
- 21:3421:34, 1 May 2024 diff hist +212 Second order linear ODE →Constant coefficient, homogeneous
- 21:3121:31, 1 May 2024 diff hist +159 Second order linear ODE →Constant coefficient, homogeneous
- 21:2821:28, 1 May 2024 diff hist +108 N Linear combination Created page with "The linear combination of any homogeneous solution is still a solution. Category:Differential Equations" current
- 21:2721:27, 1 May 2024 diff hist +792 N Second order linear ODE Created page with "Second order linear ODEs are in the following form: <math> y''+p(t)y'+q(t)y=g(t) </math> Important types of second order linear ODEs include * Homogeneous * Constant coefficients (where p and q are constants) = Initial value problem = There are two arbitrary constants in the solution of a second order linear ODE, so we need two initial conditions. <math> \begin{cases} y(t_0)=y_0\\ y'(t_0)=y_0' \end{cases} </math> = Solutions = == Constant coefficient, homogeneou..."
- 21:2121:21, 1 May 2024 diff hist +36 N First Order Scalar ODE Rice moved page First Order Scalar ODE to First order scalar ODE current Tag: New redirect
